2023-2024 Topic: Micro-Electronic Packaging

Micro-Electronic Packaging is becoming more complex and integral for increased performance and specialized applications. Advancements are needed in designing novel hardware architectures and the means to address thermal considerations in these tightly integrated chiplet and heterogeneous, 2.5D/3D packages.

For general and special purpose processor to ‘optimize’ performance, design complexity increases as advancements in hardware acceleration require moving beyond monolithic integrated circuits. Heterogenous Packaging techniques, such as multi-chip modules and 2.5/3D ICs, provide an avenue for easily integrating multiple chips into a single packaged device with notable reductions in communication delay. By integrating multiple chips onto a shared substrate containing chip-to-chip interconnect such as interposers or Through-Silicon Vias (TSV), these techniques provide flexibility in integrating chips designed in various process nodes for further optimization in cost and performance. There are three areas of interest related to enabling or facilitating these advance packaging concepts that can be pursued under this year’s Innovation Bowl.  Specific topic areas of interest are listed below followed by a more detailed discussion of each area. Participating teams will be able to ask question and interact with Radiance Subject Matter Experts on this topic for further clarification.

Please address one of the following topics:

Topic #1: Novel hardware architectures for AI/ML systems enabled by Advanced Heterogeneous Packaging

Topic #2: Methods for fast thermal evaluations of 2.5 / 3D packaging assemblies to enable parametric testing of prototype configurations

Topic #3: Thermal solutions to enable tighter integration of chiplets in Advanced Packages

Topic #1: Novel hardware architectures for AI/ML systems enabled by Advanced Heterogeneous Packaging

Artificial Intelligence/Machine Learning stands firmly as a rapidly-advancing field of study requiring and driving state-of-the-art design techniques and hardware architectures through need of specialized hardware accelerators. Initially, these improvements came in the form of domain-specific hardware such as Google’s Tensor Processing Unit [1] [4], IBM’s TrueNorth [2], and Intel’s Loihi [3]. However, as design complexity increases, advancements in hardware acceleration require moving beyond monolithic integrated circuits. Heterogenous Packaging techniques, such as multi-chip modules and 2.5/3D ICs, provide an avenue for easily integrating multiple chips into a single packaged device with notable reductions in communication delay. By integrating multiple chips onto a shared substrate containing chip-to-chip interconnect such as interposers or Through-Silicon Vias (TSV), these techniques provide flexibility in integrating chips designed in various process nodes for further optimization in cost and performance. Using these methodologies, novel architectures which reduce design complexity and cost of specialized accelerators while improving efficiency and yield will emerge. This Innovation Bowl topic involves the analysis and implementation of novel hardware architecture solutions utilizing advanced heterogenous packaging to create more efficient artificial intelligence and machine learning components.

[1] Jouppi, Norman P., et al. “In-datacenter performance analysis of a tensor processing unit.” Proceedings of the 44th annual international symposium on computer architecture. 2017.

[2] DeBole, Michael V., et al. “TrueNorth: Accelerating from zero to 64 million neurons in 10 years.” Computer 52.5 (2019): 20-29

[3] Orchard, Garrick, et al. “Efficient neuromorphic signal processing with loihi 2.” 2021 IEEE Workshop on Signal Processing Systems (SiPS). IEEE, 2021.

[4] Jouppi, Norm, et al. “Tpu v4: An optically reconfigurable supercomputer for machine learning with hardware support for embeddings.” Proceedings of the 50th Annual International Symposium on Computer Architecture. 2023.

Topic #2: Methods for fast thermal evaluations of 2.5 / 3D packaging assemblies to enable parametric testing of prototype configurations

Increasing computational requirements for Internet of Things (IoT), machine learning, and cloud computing applications cause challenges to the Moore’s Law technique of scaling semiconductor devices into smaller and more complex monolithic System-on-Chip (SoC) solutions. In advanced process nodes, standard 2D Integrated Circuits (ICs) for high-performance applications often have undesirable performance-per-watt metrics, as well as increased interconnect complexity, and interconnect delay. 2.5D and 3D integrated circuits, where multiple chips are integrated together into a shared module, present new design solutions to this problem. These systems have reduced interconnect power consumption and reduced signal delay, as well as the flexibility to use less costly semiconductor nodes for certain chips and more advanced nodes for others in the same system [1]. 2.5D technology involves side-by side integration of chips onto a shared substrate, with chips connected through bridge chip or interposer technologies [2]. 3D ICs involve vertically stacked and integrated ICs with direct connections up the hierarchy using either solder bumps or Through-Silicon Vias (TSVs). Tightly-integrating several high-performance chips onto a shared integrated substrate can create unwanted thermal stress on the system due to high power consumption in a small package. This thermal stress can cause mechanical or electrical failures in the design and is usually carefully mitigated in the design process. To reduce the overall cost of the 2.5D/3D system design, it is highly beneficial to characterize the thermal weaknesses and points of failure during the prototype stage through modeling and simulation. Power maps and thermal profiles of heterogeneously-integrated ICs can be created using multiphysics simulators and other advanced simulation and numerical methods [1] [2] [3]. This Innovation bowl topic involves the development of fast simulation techniques or fast numerical analyses to quickly evaluate the thermal characteristics of a 2.5D/3D IC to reduce the time-to-market and design cycle cost.

[1] K. Salah, “Survey on 3D-ICs thermal modeling, analysis, and management techniques,” 2017 IEEE 19th Electronics Packaging Technology Conference (EPTC), Singapore, 2017, pp. 1-4, doi: 10.1109/EPTC.2017.8277428.

[2] Y. Zhang, T. E. Sarvey and M. S. Bakir, “Thermal Evaluation of 2.5-D Integration Using Bridge-Chip Technology: Challenges and Opportunities,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 7, pp. 1101-1110, July 2017, doi: 10.1109/TCPMT.2017.2710042.

[3] M. Zhou, L. Li, F. Hou, G. He and J. Fan, “Thermal Modeling of a Chiplet-Based Packaging With a 2.5-D Through-Silicon Via Interposer,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 6, pp. 956-963, June 2022, doi: 10.1109/TCPMT.2022.3174608.

Topic #3: Thermal solutions to enable tighter integration of chiplets in Advanced Packages

Moore’s law has guided the continuous scaling of semiconductor devices to smaller and more complex process nodes. However, applications such as the Internet of Things (IoT), artificial intelligence and machine learning, as well as cloud computing applications require increasingly complex and costly Integrated Circuits (ICs) that simple transistor/process shrinking struggles to solve.  Advanced packaging techniques, such as multi-chip-modules and 2.5/3D ICs, aim to present an alternative to process node shrinking by allowing for integration of multiple chips into a package with advanced interconnect techniques to allow for fast communication between components. Such techniques for 2.5D ICs include integrating chiplets onto a shared substrate with chip-to-chip connections through bridge chip technologies or interposer technologies [1]. Additional techniques can include solder bump or Through-Silicon Via (TSV) connections made between vertically-stacked chiplets to create a 3D IC. However, densely packing high-performance chiplet components into a small, advanced package causes high power consumption in a localized area. The resulting thermal stress can cause physical defects in semiconductor material, defects in solder bump material, unacceptable noise, or electrical failures on the system. As such, managing thermal effects for an efficient, tightly-integrated package is an area of utmost concern. Mitigation techniques often include heat sinks, heat spreaders, novel thermal interface materials (TIMs), liquid cooling, and thermally-driven design techniques earlier in the IC design cycle [2]. This Innovation Bowl topic involves the analysis and implementation of novel thermal management techniques to allow for tightly-integrated chiplets in efficient heterogeneous ICs.

[1] Y. Zhang, T. E. Sarvey and M. S. Bakir, “Thermal Evaluation of 2.5-D Integration Using Bridge-Chip Technology: Challenges and Opportunities,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 7, pp. 1101-1110, July 2017, doi: 10.1109/TCPMT.2017.2710042.

[2] K. Salah, “Survey on 3D-ICs thermal modeling, analysis, and management techniques,” 2017 IEEE 19th Electronics Packaging Technology Conference (EPTC), Singapore, 2017, pp. 1-4, doi: 10.1109/EPTC.2017.8277428.